Baseline JPEG Video Decoder IP Core

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ALSE Advanced Logic Synthesis for Electronics

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Our Baseline JPEG Decoder (Decompression) IP core is capable of decoding standard JPEG-compressed images or Video on-the-fly and produce a raw video stream without any processor nor external memory. The latency is minimal. It is easily integrated in any design, with simple streaming interfaces. Can be used stand-alone or with Platform Designer.

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Key Features

Low latency, standard, compact, no external memory, JPEG Decoder

Offering Brief

Device Family	Arria® 10 SX FPGA, Cyclone® III FPGA, Cyclone® IV GX FPGA, Agilex™ 5 FPGA E-Series, MAX® 10 FPGA, Cyclone® V SX FPGA, Arria® V GZ FPGA, Agilex™ 9 FPGA Direct RF-Series, MAX® V CPLD, Agilex™ 7 FPGA I-Series, Arria® V SX FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX FPGA, Agilex™ 7 FPGA M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex™ 3 FPGA C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST FPGA, Agilex™ 5 FPGA D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex™ 7 FPGA F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status	Production
Integrated Testbench	No
Evaluation License	No
Design Examples Available	No
Demo	Yes
Compliance	No
OS Support	Windows,Linux
Development Language	Encrypted Verilog, Encrypted VHDL