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Baseline JPEG Video Decoder IP Core

ALSE Advanced Logic Synthesis for Electronics

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Our Baseline JPEG Decoder (Decompression) IP core is capable of decoding standard JPEG-compressed images or Video on-the-fly and produce a raw video stream without any processor nor external memory. The latency is minimal. It is easily integrated in any design, with simple streaming interfaces. Can be used stand-alone or with Platform Designer.

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Key Features

  • Low latency, standard, compact, no external memory, JPEG Decoder
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Demo Yes
OS Support Windows,Linux
Development Language Encrypted Verilog, Encrypted VHDL

Depends on licensing scheme selected.

Ordering Information

JPEG-D

from Direct

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Documentation & Resources

design hub icon JPEG Video Decoder
design hub icon Streaming over PLC

Market Segment and Sub-Segments

Aerospace-Avionics-252x228

Aerospace

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Aerospace

Aerospace

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Consumer-252x228

Consumer

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Consumer

Gaming

Home Audio/Video

Other Consumer

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Electronic-Warfare-252x228 (1)

Defense

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Defense

MIL COMMS

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Robotics-252x228

Industrial

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Industrial

Industrial / Manufacturing

Robotics

Vision

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