partner-offering-banner.png

Baseline JPEG Video Decoder IP Core

ALSE Advanced Logic Synthesis for Electronics

Select

Our Baseline JPEG Decoder (Decompression) IP core is capable of decoding standard JPEG-compressed images or Video on-the-fly and produce a raw video stream without any processor nor external memory. The latency is minimal. It is easily integrated in any design, with simple streaming interfaces. Can be used stand-alone or with Platform Designer.

Key Features

  • Low latency, standard, compact, no external memory, JPEG Decoder
Expand Close
Keyfeatures main image

Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available No
Demo Yes
Compliance No
OS Support Windows,Linux
Development Language Encrypted Verilog, Encrypted VHDL

Depends on licensing scheme selected.

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments