Aurora 64B/66B IP Core

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ALSE Advanced Logic Synthesis for Electronics

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Aurora 64B/66B is a lightweight and open protocol suitable for chip-to-chip, board-to-board and backplane applications using high-speed transceivers. The ALSE Aurora 64B/66B IP Core is a very compact and optimized implementation developed and verified to ensure full compatibility with the published protocol and Xilinx IP core. This ALSE IP core is available on all the Altera FPGAs that include transceivers.

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Key Features

All configurations are supported

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Arria® V GX FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Stratix® 10 AX SoC FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	Yes
Demo	No
Compliance	No
Intertop	with Xilinx IP
Latest Quartus Version Supported	25.3.1
OS Support	Windows,Linux
Development Language	Encrypted Verilog, Encrypted VHDL, Other