The AVB-Milan IP from ALSE incorporates the functionalities defined by the Avnu MILAN Specifications for End Stations and Bridged End Stations and it is currently available on the Altera Cyclone® V SoC FPGA family.
It combines a complex FPGA Hardware design (RTL) located in the programmable side of the SoC-FPGA for the very low latency and hard real time features like Ethernet packet processing, and a Software stack that runs on the ARM Multi-Processor Core System for the complex network management protocols.