JPEG-EX-F: Ultra-Fast Baseline and Extended JPEG Encoder

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Computer Aided Software Technologies, Inc (dba CAST)

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This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG encoder that can compress high pixel rate video using significantly fewer silicon resources and less power than encoders for video compression standards such as HEVC/H,265, DSC, AVC/H.264, or JPEG200.

The JPEG-EX-F encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with up to 12-bit color samples and up to four color components, in all widely-used color subsampling formats.

Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame video.

Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames...

Depending on its configuration, the encoder processes from two to 32 color samples per clock cycle, enabling it to compress UHD (4K/8K) video and/or very high frame video.

Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.

Customers with a short time to market priority can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

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Key Features

Scalable, ultra-high performance 4K/8k capable JPEG Encoder, requiring significantly lower power and fewer area than any equally fast HW video encoder.
Supporting: ISO/IEC 10918-1 Baseline & Extended Seq DCT modes, single-frame images & Motion JPEG payloads, 8/12-bit color samples, up to 4 color components.
Rate Control Options: For images, limits the size of each individual frame, while for video regulates bit rate over a number of input frames.
Interfaces: AXI Streaming pixel and compressed stream interfaces and APB Control/Status interface.
High performance: Synthesis-time configurable scalable throughput, up to 32 samples/cycle, supports UHD (4k/8K) video and/or ultra-high frame rates.
High performance: Synthesis-time configurable scalable throughput, up to 32 samples/cycle, supports UHD (4k/8K) video and/or ultra-high frame rates.

Offering Brief

Device Family	Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	Yes
Demo	No
Compliance	Yes
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted Verilog, Verilog