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ZipAccel-C: GZIP/ZLIB/Deflate Data Compression Core

Computer Aided Software Technologies, Inc (dba CAST)

Member

ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards.

The core receives uncompressed input files and produces compressed files. No post-processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input.

The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 400 Gbps are feasible and latency can be as small as a few tens of clock cycles.

ZipAccel-C offers compression efficiency practically equivalent to today’s popular deflate-based software applications. Analyzing processing speed versus compression efficiency to achieve the best trade-off for a ...

ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards.

The core receives uncompressed input files and produces compressed files. No post-processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input.

The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 400 Gbps are feasible and latency can be as small as a few tens of clock cycles.

ZipAccel-C offers compression efficiency practically equivalent to today’s popular deflate-based software applications. Analyzing processing speed versus compression efficiency to achieve the best trade-off for a specific system is facilitated by the included software model, and by support from our team of data compression experts.

ZipAccel-C has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data compression, and optionally from the task of encrypting the compressed stream.

Key Features

  • Compression Standards: Deflate (RFC-1951), ZLIB (RFC-1950), GZIP (RFC-1952).
  • LZ77 with configurable block and search window size. Static and dynamic Huffman. Optional stored deflate blocks. Dynamic mode selection.
  • Fine-tune Throughput, Compression Efficiency, and Latency to match application requirements. Silicon requirements start from less than 100k gates. Under 40 clock cycles for Static Huffman.
  • Configuration options such as Search engine and Huffman encoder architecture, History search window size. and Deflate block size.
  • Processor-free, standalone operation.
  • Optionally integrated with DMA, encryption or other cores from CAST.
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Verilog/System Verilog, Encrypted Verilog/System Verilog or netlist

Comprehensive documentation

Sample simulation and synthesis scripts

Verilog testbenches

Bit-Accurate Model

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments