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AES-XTS: Storage Encrypt/Decrypt Engine

Computer Aided Software Technologies, Inc (dba CAST)

Member

The AES-XTS encryption IP core implements hardware encryption/decryption for sector-based storage data. It uses the AES block cipher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths.

Two architectural versions are available to suit system size and throughput requirements. The High Throughput XTS-X is more compact and can process 128 bits/cycle independent of the key size. The Higher Throughput XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path.

XTS (XEX-based Tweaked Codebook Mode with Ciphertext Stealing) is a mode of AES that has been specifically designed to encrypt fixed-size data where a possible threat has access to the stored data.

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Key Features

  • Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm, implemented according to the IEEE P1619™/D16 standard, and is NIST-Validated.
  • Capable of processing 128 bits/cycle, employing user-programmable key size of 128 or 256 bits and arbitrary IV length.
  • Two architectural versions available. AES-XTS-X version, smaller, able to process 128 bits/cycle. AES-XTS-X2 version able to process 256 bits/cycle.
  • Easy integration & implementation (integrated key expansion, fully synchronous) & simple I/F that can be bridged to AMBA or integrated with a DMA.
  • Available in VHDL or Verilog source code format, or as a targeted FPGA netlist.
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Compliance Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Verilog/System Verilog, Encrypted Verilog/System Verilog, VHDL, Encrypted VHDL, or FPGA netlist

System Verilog testbench

Comprehensive documentation

Sample synthesis and simulation scripts

Software model

Ordering Information

AES-XTS

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