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SHA-256: 256-bit SHA Secure Hash Crypto Engine

Computer Aided Software Technologies, Inc (dba CAST)

Member

The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (2^64 – 1) bits.

Developed for easy reuse in ASIC and FPGA applications, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics. Support for AMBA bus interfaces and integration with an external DMA are available as options

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Key Features

  • NIST-Validated SHA-256 implementation compliant to FIPS 180-4
  • Input length up to (2^64 – 1) bits
  • Processes 512-bit blocks in 65 cycles, delivers over 10 Gbps on modern ASICs, and allows throughput scaling with multiple clocked instances.
  • Small Silicon footprint: 15k-20k Gates
  • Fully synchronous SHA-256 core with single-clock domain, scan-ready, LINT-clean, reusable design, simple I/O, optionally bridged to AMBA™ or DMA.
  • Available in VHDL or Verilog source code format, or as a targeted FPGA netlist
  • Complete deliverables include test benches, C model, and test vector generator
  • Multiple times production proven in ASIC and FPGA designs
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Compliance Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Verilog/System Verilog, Encrypted Verilog/System Verilog, VHDL, Encrypted VHDL, or FPGA netlist

System Verilog testbench

Comprehensive documentation

Sample synthesis and simulation scripts

Software model

Ordering Information

SHA-256

from Direct

Get Pricing and Availability

Documentation & Resources

design hub icon SHA-256 datasheet

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