The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.
Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB.
The core works with a pre-expanded key, or with optional key expansion logic.
The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.