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UDP/IP Offload Engine

Chevin Technology Limited

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User Datagram Protocol (UDP/IP) is a communications protocol used for establishing connections between applications on the Internet. The UDP Protocol is a transport layer that runs on top of the Internet Protocol (IP) Layer and is used for connections where high sustained throughput is a priority and some data loss is expected, such as with video and audio streaming. Chevin Technology’s 10G /25G/40G/100G UDP Ethernet IP core for FPGAs has low latency and bandwidth overhead, as it sends packets of data without confirming receipt. De-fragmentation is available as an option, so large UDP datagrams can be easily sent and received. The UDP IP core provides individual port numbers to differentiate between user requests, and receipt of data is verified using the checksum functionality. Chevin Technology’s 10G /25G/40G/100/200G UDP Ethernet IP core is configurable for FPGAs and simplifies integration by handling the complete Ethernet frame assembly. Chevin Technolog...

User Datagram Protocol (UDP/IP) is a communications protocol used for establishing connections between applications on the Internet. The UDP Protocol is a transport layer that runs on top of the Internet Protocol (IP) Layer and is used for connections where high sustained throughput is a priority and some data loss is expected, such as with video and audio streaming. Chevin Technology’s 10G /25G/40G/100G UDP Ethernet IP core for FPGAs has low latency and bandwidth overhead, as it sends packets of data without confirming receipt. De-fragmentation is available as an option, so large UDP datagrams can be easily sent and received. The UDP IP core provides individual port numbers to differentiate between user requests, and receipt of data is verified using the checksum functionality. Chevin Technology’s 10G /25G/40G/100/200G UDP Ethernet IP core is configurable for FPGAs and simplifies integration by handling the complete Ethernet frame assembly. Chevin Technology’s UDP IP core is a mature IP core with proven success in customers’ projects. Reference designs are available for various boards to assist with integration and we offer our customers bespoke, expert engineering support packages to help meet their project goals. A simple AXI4 streaming interface is all that is required to start sending and receiving UDP datagrams, and only the user data payload is exchanged between the application and the UDP core. For a single port application the port number can be set to a constant, hard coded or software configurable. A multi-port application is supported by a single UDP IP core by using the TDEST sideband embedded in the streaming interface.

Key Features

  • AXI4s MAC & Application Interfaces
  • De-fragmentation option available
  • Designed to UDP specification RFC768
  • Compose/Decompose complete UDP Datagrams
  • IP frame Checksum Generator/Checker
  • Jumbo frame support up to 32k
  • Consistently low and predictable latency with zero frame jitter
  • 1-64k Ports (configurable ports & filters)
  • Detailed traffic analysis statistics collection
  • ARP/ICMP layers for complete FPGA hosted application with ARP and ICMP “ping”
  • Integrated Streaming FIFO
  • Flow Control between MAC/User logic
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Offering Brief

Offering Brief

Device Family Cyclone® III FPGA, Agilex™ 9 FPGA Direct RF-Series, MAX® V CPLD, Stratix® IV E FPGA, Stratix® IV GX FPGA, MAX® 10 FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.3.1
Development Language Encrypted VHDL

RTL – encrypted source/netlist , Documentation – Data Sheet and User Guide, Simulation – Test Bench and example use cases with vector generation

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