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TCP/IP Offload Engine

Chevin Technology Limited

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The TCP/IP (Transmission Control Protocol/ Internet Protocol) is an Ethernet IP stack for FPGAs that incorporates both the transport and internet layer protocols to deliver reliable, end to end network communications using the internet or on private networks. The TCP/ IP stack can be used with Chevin Technology’s 10G/25G/40G/100G Ethernet IP cores for dependable, low-latency connectivity in any FPGA using a minimum of FPGA resources.

Chevin Technology’s TCP/IP Offload Engine is an FPGA Synthesisable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution. Chevin Technology’s TCP/IP offloads the TCP protocol using fast and efficient logic for checksum calculation. Valuable resources in your application are freed up by the TCP/IP which offloads the entire TCP stack onto FPGA logic. Using the FPGA to analyse packets instead of the CPU significantly increases data transfer time and consistently reduces jitter.

The TCP/IP is easily integrated...

The TCP/IP (Transmission Control Protocol/ Internet Protocol) is an Ethernet IP stack for FPGAs that incorporates both the transport and internet layer protocols to deliver reliable, end to end network communications using the internet or on private networks. The TCP/ IP stack can be used with Chevin Technology’s 10G/25G/40G/100G Ethernet IP cores for dependable, low-latency connectivity in any FPGA using a minimum of FPGA resources.

Chevin Technology’s TCP/IP Offload Engine is an FPGA Synthesisable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution. Chevin Technology’s TCP/IP offloads the TCP protocol using fast and efficient logic for checksum calculation. Valuable resources in your application are freed up by the TCP/IP which offloads the entire TCP stack onto FPGA logic. Using the FPGA to analyse packets instead of the CPU significantly increases data transfer time and consistently reduces jitter.

The TCP/IP is easily integrated alongside other protocols to provide an easy path for the development of TCP enabled FPGA applications.

Chevin Technology offer flexible licensing terms and engineering support packages to suit the requirements of each customer.

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Key Features

  • 1 to 256/1k/64k Simultaneous connections
  • All-RTL send/receive for extremely low latency
  • Server/Client roles, configurable per connection
  • Automatically establish & tear-down connections
  • ARP/ICMP layers for complete FPGA hosted application with ARP and ICMP “ping”
  • Programmable per connection receive/congestion window
  • 64-bit AXI4 Send & Receive streams @ 156.25 MHz / 390MHz
  • Internal RAM or External DDR3 buffers
  • Configurable TX & RX buffer size: 4KiB-2GiB
  • Monitoring function, per-session statistics
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 9 FPGA Direct RF-Series, Cyclone® III FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.3.1
Development Language Encrypted VHDL

RTL – encrypted source/netlist , Documentation – Data Sheet and User Guide, Simulation – Test Bench and example use cases with vector generation

Ordering Information

CT-TCP_OFFLOAD_ENGINE

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Documentation & Resources

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