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Unmanaged Ethernet Switch IP - 1G, 1G/10G, 10G, 10G/25G

Comcores ApS

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Comcores Ethernet Unmanaged Switch family IP cores provide a variety of configurations, including 1G, 1G/10G, 10G, and 10G/25G options. These IP cores are size-optimized implementations of non-blocking crossbar switches, designed to support wire-speed packet processing and forwarding. These switches feature FCS validation/recalculation, MAC learning/forwarding/aging, VLAN tagging, and they implement a store-and-forward switching architecture. The number of ports is configurable at compile time, making the solution highly flexible.

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Key Features

  • Automatic MAC address learning and aging
  • Support programmable static forwarding entries
  • Ethernet Multicast support
  • Full duplex Ethernet interfaces
  • Supports Access port VLAN and Trunk port VLAN operation
  • Configurable for up to 16 + 4 ports at compile time
  • Supports configurable queuing behaviour, including round-robin and fair queuing
  • Compatible with GMII, RGMII, XGMII, and XXVMII interfaces for seamless connection to external Physical Layer devices (PHYs)
  • Easy integration with standard Xilinx AXI4 Lite control interface
  • Can be implemented with or without an external microcontroller
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Cyclone® 10 GX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language Encrypted VHDL, VHDL

Solid documentation, including User Manual and Release Note

Simulation Environment, including Simple Testbed, Test case and Test Script

Programming Register Specification

Timing Constraints in Synopsys SDC format

Access to support system and direct support from Comcores Engineers

Synopsys SGDC Files (optional)

Synopsys Lint, CDC and Waivers (optional)

Ordering Information

CM_ETHSWI_01_B_F

from Direct

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