Creonic DVB-S2 Demodulator

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Creonic GmbH

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DVB-S2 (Digital Video Broadcast – Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first standard of the second generation DVB standards (DVB-S2/DVB-T2/DVB-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 high performance demodulator IP core performs all tasks of an inner receiver. Its output perfectly fits the DVB-S2 forward error correction IP core from Creonic that implements LDPC and BCH decoding.

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Key Features

Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2) Supports ACM, VCM, CCM mode for broadcasting
Support for QPSK and 8-PSK modulations. 16-APSK and 32-APSK
Support for short blocks (16200 bits) and long blocks (64800 bits)
Output of XFECFRAMEs for further processing by the Creonic DVB-S2 FEC Decoder IP core

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® III FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	No
Demo	No
Compliance	No
Latest Quartus Version Supported	22.4.0
Development Language	C/C++, Verilog, VHDL

Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model

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