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Creonic SDA OCT V 3.0 Encoder and Decoder

Creonic GmbH

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The Creonic SDA OCT V3.0 Encoder handles the construction of Over-The-Air (OTA) frames as indicated in the standard, a preamble followed by a header and payload data, with both fields being protected by cyclic redundancy check (CRC) and forward error correction (FEC). The Creonic SDA OCT V3.0 Decoder performs the synchronization of the Over-The-Air (OTA) frame and then decodes the header and payload data within the frame.

Key Features

  • Compliant with "Optical Communications Terminal (OCT) Standard Version 3.0, Document ID: SDA-9100-001-05, August 2021"
  • Compliant with "Optical Communications Terminal (OCT) Standard Version 3.1.0, Document ID: SDA-9100-001-08, March 2024"
  • Compliant with "Optical Communications Terminal (OCT) Standard Version 4.0.0, Document ID: SDA-9100-001-09, August 2024"
  • Support for payload code rates 11/13, 22/29, 2/3, 1/2, and uncoded data
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 22.4.0
Development Language C/C++, Verilog, VHDL

Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model​

Ordering Information

Documentation & Resources

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