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DVB-RCS2 Multi-Carrier Receiver

Creonic GmbH

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The Creonic DVB-RCS2 Multi-Carrier Receiver IP core supports multiple frequency time domain multiple access (MF-TDMA), performs all tasks of a DVB-RCS2 receiver including carrier separation, baseband conversion, demodulation, and turbo decoding. It can process intermediate frequency (IF) real signal with center IF frequencies between 0 and 100 MHz. The Creonic turbo decoder is included in the receiver to provide users with Frame PDUs at the output.

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Key Features

  • Compliant with ETSI EN 301 545-2 (DVB-RCS2)
  • Support for Linear Modulation Bursts of Table A-1
  • Optional support for Spread-spectrum Linear Modulation Burst waveforms of Table A-2
  • Support for BPSK, QPSK, 8-PSK, 16-QAM
  • Supports real, intermediate frequency signal at input
  • Supports 32 carriers at aggregate symbol rate of 50 MSymbols/s, sample rate of 200 MSamples/s
  • Supports symbol rate per carrier from 200 kSymbols/s to 12.5 MSymbols/s at an input rate of 200 MSamples/s
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 22.4.0
Development Language C/C++, Verilog, VHDL

Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model​

Ordering Information

Creonic DVB-RCS2 Multi-Carrier Receiver

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Documentation & Resources

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Market Segment and Sub-Segments

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Aerospace

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Aerospace

Aerospace

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Wireless

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Wireless

Baseband

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