Design Gateway’s TOE1G-IP core provides a complete TCP Offload Engine (TOE) solution, implemented entirely in hardware for Altera FPGAs. This IP core enables high-throughput network communication by offloading the entire TCP/IP stack to the FPGA fabric. This eliminates the need for external processors or software-based protocol handling, making the TOE1G-IP ideal for real-time and high-performance systems such as remote data logging systems, industrial control systems, and defense applications where consistent and reliable data transfer is essential.
The TOE1G-IP supports key TCP functions including connection setup and termination, retransmission control, and flow management—all handled autonomously in hardware. It features a user-friendly FIFO interface for data and a register-based control interface, ensuring seamless integration. Supporting both client and server roles, the core provides flexibility for a wide range of applications. Reference designs and e...
Design Gateway’s TOE1G-IP core provides a complete TCP Offload Engine (TOE) solution, implemented entirely in hardware for Altera FPGAs. This IP core enables high-throughput network communication by offloading the entire TCP/IP stack to the FPGA fabric. This eliminates the need for external processors or software-based protocol handling, making the TOE1G-IP ideal for real-time and high-performance systems such as remote data logging systems, industrial control systems, and defense applications where consistent and reliable data transfer is essential.
The TOE1G-IP supports key TCP functions including connection setup and termination, retransmission control, and flow management—all handled autonomously in hardware. It features a user-friendly FIFO interface for data and a register-based control interface, ensuring seamless integration. Supporting both client and server roles, the core provides flexibility for a wide range of applications. Reference designs and evaluation files are available