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AES 256 XTS STG IP for NVMe Gen3

DesignGateway Co., Ltd.

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As storage performance continues to accelerate, the need for high-speed, real-time data encryption has become a critical challenge. To meet this demand, Design Gateway’s AES-XTS IP core is optimized for NVMe PCIe Gen3 SSDs, delivering advanced data protection without compromising system speed or efficiency. Built entirely in hardware logic, this IP core accelerates encryption and decryption processes, ensuring minimal latency and maximum throughput. It enables seamless integration into ultra-high-speed storage systems while maintaining robust data security—making it ideal for enterprise storage, secure recording, and high-performance computing environments. With support for real-time processing at PCIe Gen3 speeds, the AES-XTS IP core is a powerful solution for organizations looking to protect sensitive data while leveraging the full potential of next-generation NVMe storage.

Key Features

  • High-speed data transfer and real-time encryption/decryption up to 4.4 GB/s
  • Optimized for PCIe Gen3 NVMe SSD applications
  • Ideal for data security in mission-critical environments like industrial and military applications
  • Ensures secure data recording with AES-XTS encryption technology
  • Proven encryption performance for secure storage
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Offering Brief

Offering Brief

Device Family Arria® 10 SX FPGA, Cyclone® 10 GX FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo Yes
Compliance No
Hardware Platforms Supported Arria® 10 SX SoC Development Kit
Latest Quartus Version Supported 23.1.0
Development Language Encrypted VHDL

Encrypted IP core

Reference Designs Quartus Project

Ordering Information

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