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DMESCC - Multiprotocol Enhanced Serial Communication Controller

DCD-SEMI

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DMESCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit microprocessors. DMESCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM® Bisync, and synchronous bit-oriented protocols such as HDLC and SDLC. The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The DMESCC also has facilities for modem control in both channels.

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Key Features

  • Dual-Channel: A, B
  • Configuration capability
  • Asynchronous mode: Asynchronous (x16, x32, or x64 clock), Isochronous (x1 clock)
  • Character-Oriented mode: Monosynchronous, Bisynchronous, External Synchronous
  • Bit-Oriented mode: SDLC/HDLC, SDLC/HDLC Loop
  • Complete status reporting capabilities
  • Receiver data FIFO and Error FIFO
  • SDLC Frame FIFO
  • Transmitter FIFO
  • Data encoder\decoder: NRZ, NRZI, FM0, FM1, Manchester (require external logic)
  • Line break generation and detection
  • Internal diagnostic capabilities: Loop-back controls for communications link fault isolation, Auto Echo, Break, parity, overrun, framing error simulation
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

HDL Source Code

Testbench environment - automatic simulation macros, tests with reference responses

Synthesis scripts

Technical documentation

12 months of technical support

Ordering Information

DMESCC

from Direct

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Documentation & Resources

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