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DSENT - Cutting-Edge SENT Protocol IP Core for Automotive Communication

DCD-SEMI

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The DSENT, a hardware implementation of the Single Edge Nibble Transmission (SENT) protocol controller. Designed to comply with the SAE-J2716 standard, DSENT delivers a robust, low-cost solution for reliable data communication between automotive sensors and central units such as Engine Control Units (ECUs).

The SENT protocol is a single-wire communication system optimized for transmitting signal values through precise time measurement between two falling signal edges. DSENT offers hardware-based efficiency, enabling seamless data exchange either as a transmitter in sensors or a receiver in central units.

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Key Features

  • Versatility in Communication: Supports Fast and Slow Channel transmission or reception.
  • Automatic Data Rate Synchronization: Maintains stable data exchange despite variations in clock accuracy.
  • Customizable Data Length: Configurable from 1 to 6 nibbles for enhanced flexibility.
  • Advanced Error Detection: Features optional automatic CRC error detection and Frame Error.
  • Hardware CRC calculation in Transmit mode.
  • Pause Pulse Support: Includes optional Pause Pulse Period functionality for operational efficiency.
  • Master Trigger Pulse Support: Enables communication with up to four sensors over a single wire.
  • Technology Independence: Fully synthesizable and implementable across various process technologies.
  • A 56-tick calibration/synchronization pulse.
  • Status and communication nibbles spanning 12 to 27 ticks.
  • Up to six data nibbles of similar durations.
  • A CRC checksum nibble for data validation.
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, MAX® V CPLD, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Verilog

HDL Source Code

Testbench environment - automatic simulation macros, tests with reference responses

Synthesis scripts

Technical documentation

12 months of technical support

Ordering Information

DSENT

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Documentation & Resources

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Market Segment and Sub-Segments

Software-Defined-Vehicle-252x228

Transportation

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Transportation

Automotive (Passenger Vehicles)

Charging Infrastructure

Non-Automotive Transportation

Transportation Infrastructure (non-charging)

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