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IntelliProp AES Encryption with XTS IP Core (IPC-BL120A-ZM)

IntelliProp: Experts in Memory and Data Storage IP

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In the world of high-capacity storage, protecting the physical media is the last line of defense. The IPC-BL120A-ZM stands as the industry's "Commander" of secure data-at-rest, utilizing the AES-XTS (XEX Tweakable Block Cipher with Ciphertext Stealing) mode. Unlike standard AES modes, XTS is specifically designed for block storage, using a "tweak" based on the logical block address (LBA) to ensure that the same data stored in different locations results in unique ciphertext.

This core allows engineers to implement FIPS-compliant, hardware-based encryption that is fully transparent to the host. It is specifically engineered to handle the unique requirements of sector-based storage—including the ability to handle data units that are not a multiple of the block size—ensuring that every byte of a drive is secured without the overhead of software-level encryption.

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Key Features

  • Algorithm: NIST and IEEE compliant AES-XTS mode.
  • Key Support: Supports 128-bit and 256-bit AES keys (XTS-256 and XTS-512).
  • Efficiency: Integrated ciphertext stealing for handling non-standard sector sizes.
  • Performance: Pipelined architecture for high-frequency timing closure in Altera fabrics.
  • Transparency: No custom drivers required; appears as a standard block device to the host.
  • Scalability: Easily scalable for multi-channel and multi-namespace NVMe architectures. Gemini is AI and can make mistakes.
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Offering Brief

Offering Brief

Device Family Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® V GX FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Hardware Platforms Supported Agilex™ 7 FPGA Starter Kit
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Encrypted Verilog RTL

ModelSim/Questa verification models and NIST/IEEE 1619 test vectors

Reference Design demonstrating transparent sector-based encryption

Synthesis and Place-and-Route scripts for Altera Quartus Prime Pro

Technical manual covering XTS implementation and tweak management

Ordering Information

IPC-BL120-ZM

from Direct

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