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IntelliProp AES-CTR Encryption IP Core (IPC-BL204A-ZM)

IntelliProp: Experts in Memory and Data Storage IP

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In modern high-bandwidth systems, data cannot wait for a sequential chain. The IPC-BL204A-ZM stands as the industry's "Commander" of streaming security, utilizing the AES Counter (CTR) mode to provide robust, NIST-compliant encryption without the processing dependencies of traditional modes. By encrypting a successive counter rather than the data itself, CTR mode allows for the encryption and decryption of data blocks in any order, making it uniquely suited for high-speed Altera-based architectures like Agilex 7 and 9.

This core allows engineers to implement a high-performance security layer that supports random access to encrypted data—a critical feature for high-speed SSD controllers and multi-channel networking appliances. It is specifically engineered to eliminate the "stalls" associated with feedback-based encryption, ensuring that line-rate performance is maintained even under the heaviest data loads.

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Key Features

  • Algorithm: NIST-compliant AES Counter (CTR) mode.
  • Performance: Fully pipelined architecture for maximum throughput and frequency.
  • Efficiency: High logic utilization efficiency for multi-channel implementations.
  • Flexibility: Supports 128-bit and 256-bit key lengths.
  • Architecture: Zero block-to-block dependencies for out-of-order data processing.
  • Interface: Industry-standard streaming interface for seamless integration into AXI or Avalon-based systems.
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Offering Brief

Offering Brief

Device Family Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® V GX FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Encrypted Verilog RTL

ModelSim/Questa verification models and NIST-standard test vectors

Reference Design demonstrating high-speed streaming encryption

Synthesis and Place-and-Route scripts for Altera Quartus Prime Pro

Technical manual covering AES-CTR implementation and counter management

Ordering Information

IPC-BL204A-ZM

from Direct

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