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IntelliProp AES-ECB 256 Bit Encryption IP Core (IPC-BL166A-ZM)

IntelliProp: Experts in Memory and Data Storage IP

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In the world of high-speed data processing, raw performance and block-level security are essential. The IPC-BL166A-ZM stands as the industry's "Commander" of block encryption, providing a robust, NIST-compliant implementation of the AES 256-bit Electronic Codebook (ECB) mode. Because ECB mode processes each block of data independently, it is uniquely suited for Altera-based architectures that require massive parallelism and ultra-high clock frequencies.

By providing a "Gold Standard" for 256-bit block encryption, it allows engineers to implement a high-speed cryptographic engine that can be used directly for specific data patterns or as the underlying transform for custom proprietary modes. It is specifically engineered for high-bandwidth applications where the ability to encrypt data blocks in any order—without the chaining dependencies of other modes—is critical for system throughput.

Key Features

  • Algorithm: NIST-compliant AES Electronic Codebook (ECB) mode.
  • Key Strength: Full 256-bit key support for maximum security longevity.
  • Throughput: Fully pipelined architecture for maximum clock frequency.
  • Flexibility: Independent encryption and decryption cores available.
  • Architecture: Zero dependencies between blocks, enabling out-of-order processing.
  • Interface: Simple, non-streaming or streaming interfaces for easy integration into custom wrappers.
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Offering Brief

Offering Brief

Device Family Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® V GX FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Encrypted Verilog RTL

ModelSim/Questa verification models and NIST-standard test vectors

Synthesis and Place-and-Route scripts for Altera Quartus Prime Pro

Reference Design demonstrating parallel block encryption

Technical manual covering AES-256 block transform implementation

Ordering Information

Market Segment and Sub-Segments