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IntelliProp AES-GCM Encryption IP Core (IPC-BL166A-ZM)

IntelliProp: Experts in Memory and Data Storage IP

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In the era of advanced cyber threats, encryption alone is no longer enough. The IPC-BL166A-ZM stands as the industry's "Commander" of authenticated security, utilizing the AES-GCM (Galois/Counter Mode) algorithm to provide both high-speed data confidentiality and a cryptographically strong integrity check. Unlike standard AES modes, GCM allows for the detection of unauthorized modifications to the data stream in real-time.

It is specifically engineered for high-bandwidth Altera-based systems, such as secure networking (MACsec/IPsec) and high-speed storage backplanes, where data must be protected and verified at line rate. By providing a "Gold Standard" for authenticated encryption, it allows engineers to secure sensitive data paths without introducing the latency or complexity associated with multi-stage software authentication.

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Key Features

  • Algorithm: AES-GCM (128-bit or 256-bit key support).
  • Functionality: Simultaneous encryption and authentication tag generation.
  • Performance: Pipelined architecture for high-frequency timing closure.
  • Versatility: Supports Additional Authenticated Data (AAD) for header protection.
  • Standard Interface: Clean, streaming interface for seamless integration with AXI-based systems.
  • Security: Robust protection against bit-flipping and tampering attacks.
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Offering Brief

Offering Brief

Device Family Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® V GX FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Hardware Platforms Supported Agilex™ 7 FPGA Starter Kit
Latest Quartus Version Supported 25.3.0
OS Support Algorithm: AES-GCM (128-bit or 256-bit key support).
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Encrypted Verilog RTL

ModelSim/Questa verification models and NIST-based test vectors

Reference Design demonstrating authenticated data flow

Synthesis and Place-and-Route scripts for Altera Quartus Prime Pro

Technical manual covering AES-GCM implementation and GMAC tag handling

Ordering Information

IPC-BL166A-ZM

from Direct

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