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IntelliProp ECC with BCH Algorithm (Single code; Single Correction) IP Core (IPC-BL119A-ZM)

IntelliProp: Experts in Memory and Data Storage IP

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In high-speed storage and communication environments, timing is everything. While modern NAND often demands heavy multi-bit correction, the IPC-BL119A-ZM stands as the industry's "Commander" of resource-efficient reliability. It is specifically engineered for systems where a tiny logic footprint and deterministic, single-digit nanosecond timing are non-negotiable.

By providing a hardware-level "Gold Standard" for single-bit correction (SEC) and double-bit error detection (DED), this core allows Altera engineers to guarantee data integrity without sacrificing the performance or fabric space of their primary application. It operates in-line with the data path to detect and repair errors in real-time, making it an essential component for industrial, medical, and aerospace applications using SLC NAND flash or SRAM.

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Key Features

  • Algorithm: Robust BCH implementation for 1-bit correction/2-bit detection.
  • Throughput: Full line-rate processing with no wait states during encoding.
  • Efficiency: Extremely low logic gate count and minimal internal memory usage.
  • Flexibility: Highly adjustable block sizes (e.g., 512B or 4KB) to match various memory standards.
  • Standard Interface: Simple, easy-to-integrate streaming data interface.
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Offering Brief

Offering Brief

Device Family Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® V GX FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Compliance Yes
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Encrypted Verilog RTL

ModelSim/Questa verification models and automated testbench

Reference Design demonstrating ECC insertion in a standard data path

Synthesis and Place-and-Route scripts for Altera Quartus Prime Pro

Comprehensive Technical Manual with Galois Field (GF) configuration tables

Ordering Information

IPC-BL119A-ZM

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