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IntelliProp SATA AHCI Host IP Core with AES/XTS (IPC-SA156A-1-HI)

IntelliProp: Experts in Memory and Data Storage IP

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The IPC-SA156A-1-HI provides a complete Serial-ATA (SATA) host interface solution, enabling seamless connection to high-throughput SSDs and HDDs. By implementing the industry-standard Advanced Host Controller Interface (AHCI), it ensures compatibility with standard OS drivers (Linux, Windows) and simplifies system integration. The core integrates a hardware-accelerated AES-XTS encryption engine, allowing for full-disk encryption with zero CPU overhead. This makes it ideal for embedded systems requiring both high-speed data acquisition and rigorous security standards.

Key Features

  • Compliance: Fully compliant with SATA 1.5, 3.0, and 6.0 Gb/s specifications (SATA 3.3).
  • Standard Interface: AHCI v1.3.1 compliant for "plug-and-play" driver support.
  • Advanced Security: Integrated 128/256-bit AES-XTS encryption/decryption.
  • Efficiency: High-speed DMA engine with scatter/gather support.
  • Low Power: Supports SATA power management features including Partial, Slumber, and DEVSLP modes.
  • Robustness: Built-in Self-Test (BIST) for easy field diagnostics and reliability.
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Offering Brief

Offering Brief

Device Family Agilex™ 5 FPGA D-Series, Agilex™ 7 FPGA F-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Cyclone® V GX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Encrypted Verilog RTL

ModelSim/Questa verification models and testbenches

Reference Design and synthesis/Place-and-Route scripts

Comprehensive User Documentation

Constraint files specific to the target Altera FPGA family

Ordering Information

Market Segment and Sub-Segments