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IntelliProp SATA Bridge Platform (IPP-SA143A-BR)

IntelliProp: Experts in Memory and Data Storage IP

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The IPP-SA143A-BR is the foundational SATA-to-SATA bridge in the IntelliProp catalog. It is engineered to provide an industry-compliant link between a SATA host and a SATA target device, handling all Physical, Link, and Transport layer protocol requirements entirely in hardware.

This core is ideal for applications requiring a simple, reliable bridge for protocol extension, signal conditioning, or speed adaptation. By offloading the entire SATA stack to RTL, the IPP-SA143A-BR ensures deterministic performance and eliminates the need for software development or CPU intervention. It is optimized for the full range of Altera FPGA families, providing a low-risk, power-efficient solution for industrial and enterprise storage connectivity.

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Key Features

  • Full SATA 3.2 Compliance: Supports 1.5, 3.0, and 6.0 Gb/s speeds.
  • All-Hardware Datapath: Zero firmware required; no embedded processor overhead.
  • Independent Speed Negotiation: Smart logic allows host and device to operate at different SATA generations if necessary.
  • Native Command Queuing (NCQ): Full support for advanced drive performance features.
  • Silicon-Proven Logic: Verified across multiple Altera FPGA generations and hundreds of drive models.
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Offering Brief

Offering Brief

Device Family Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Cyclone® V GX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Hardware Platforms Supported Agilex™ 7 FPGA Starter Kit
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

SATA Bridge IP Core: Encrypted RTL (Verilog/VHDL) for Altera Quartus Prime.

Standard Testbench: Basic simulation environment for link verification.

Reference Design: A working Altera FPGA project showing a basic host-to-drive bridge.

Technical Documentation: User Guide and Pin-out Specifications.

Ordering Information

IPP-SA143A-BR

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