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IntelliProp SATA Bridge Platform with Hardware Datapath IP Core (IPP-SA143A-1BR)

IntelliProp: Experts in Memory and Data Storage IP

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The IPP-SA143A-1BR combines the reliability of a silicon-proven SATA bridge with a flexible, transparent hardware "Sandbox." This architecture is specifically designed for engineers who need to intercept the data stream between a host and a device to perform real-time processing—such as proprietary data filtering, custom header insertion, or hardware-based telemetry—without the overhead of a CPU or firmware.

By utilizing a cut-through FIFO architecture, the core ensures that custom logic does not create a bottleneck, maintaining maximum SATA Gen 3 throughput. Optimized for Altera Agilex, Stratix, and Arria FPGA families, the IPP-SA143A-1BR is a premier choice for developing specialized storage appliances, secure data gateways, and advanced laboratory test equipment.

Key Features

  • Integrated Hardware Sandbox: Dedicated RTL area for real-time, inline data manipulation.
  • Full 6Gb/s Throughput: Sustained performance across SATA Gen 1, 2, and 3.
  • All-Hardware Architecture: No firmware or embedded processor required for protocol or data path management.
  • Independent Speed Negotiation: Host and target ports can sync at different speeds (e.g., 6G Host to 3G Device).
  • Low Latency Cut-Through: Minimal impact on command and data overhead.
  • SATA 3.2 Industry Compliant: Supports NCQ, 48-bit LBA, and all standard SATA command sets.
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Offering Brief

Offering Brief

Device Family Agilex™ 7 FPGA F-Series, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Cyclone® V GX FPGA, Stratix® 10 AX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

SATA Bridge + Hardware Datapath IP Core: Encrypted RTL for Altera Quartus Prime.

Sandbox Integration Templates: Documentation and "hooks" for easy RTL insertion.

Comprehensive UVM Testbench: Includes host and device models with specific monitoring for the Sandbox path.

Reference Design: A complete Altera FPGA example project demonstrating "bump-in-the-wire" logic.

Technical Documentation: Detailed User Guide, Register Maps, and Sandbox Integration Guide.

Ordering Information

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