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IntelliProp SATA Bridge Platform with Hardware Datapath with AES IP Core (IPP-SA143A-2BR)

IntelliProp: Experts in Memory and Data Storage IP

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The IPP-SA143A-2BR is a silicon-proven SATA-to-SATA bridge designed for mission-critical applications requiring both high-speed security and design flexibility. This IP core integrates a robust AES encryption engine directly into the hardware path, ensuring that all data transferred between the host and drive is encrypted or decrypted in real-time with zero impact on throughput.

Beyond security, the "Hardware Datapath" architecture provides a dedicated RTL area (Sandbox) where developers can insert proprietary algorithms—such as data compression, unique filtering, or custom telemetry—without disturbing the underlying SATA protocol. Optimized for Altera Agilex and Stratix 10 FPGA families, the IPP-SA143A-2BR is an ideal platform for building secure SSDs, encrypted storage arrays, and high-reliability aerospace or defense storage systems.

Key Features

  • Integrated AES Engine: Supports high-strength hardware encryption (e.g., AES-256) at line speeds.
  • Hardware Datapath (Sandbox): Dedicated RTL area for custom "bump-in-the-wire" logic insertion.
  • Full 6Gb/s Performance: Sustained throughput for SATA Gen 1, 2, and 3 without performance degradation.
  • Protocol Transparency: Handles all mandatory SATA 3.2 features including NCQ and 48-bit LBA.
  • Independent Link Negotiation: Host and Device ports can negotiate speeds independently for maximum compatibility.
  • Low Latency Cut-Through: Optimized internal FIFO architecture minimizes command overhead and data path delay.
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Offering Brief

Offering Brief

Device Family Agilex™ 7 FPGA F-Series, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Cyclone® V GX FPGA, Stratix® 10 GX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Hardware Platforms Supported Agilex™ 7 FPGA Starter Kit
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

SATA Bridge + AES IP Core: Encrypted RTL (Verilog/VHDL) for Altera Quartus Prime Pro.

Encryption Key Management: Standardized RTL hooks for secure key storage and rotation.

Advanced UVM Testbench: Comprehensive simulation environment with SATA host, device, and security validation models.

Reference Design: Complete Altera FPGA project showcasing an encrypted "bump-in-the-wire" bridge.

Detailed Documentation: User Guides, AES performance data, and Register Maps.

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