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IntelliProp SATA Port Multiplier with Sandbox (IPP-SA128A-PM)

IntelliProp: Experts in Memory and Data Storage IP

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The IPP-SA128A-PM provides a robust, silicon-proven solution for expanding SATA connectivity within Altera FPGA designs. Utilizing Command-Based Switching, it allows a single host port to manage multiple downstream SATA targets effectively.

The core’s standout feature is the integrated "Sandbox"—a transparent hardware "hook" that allows engineers to insert custom RTL logic directly into the data path. This enables line-speed applications such as custom encryption, data filtering, or proprietary telemetry without interfering with the underlying SATA protocol. Optimized for Altera Agilex and Stratix architectures, the core ensures high-throughput and deterministic performance for advanced storage arrays and secure data-logging systems.

Key Features

  • SATA 3.2 Compliant: Supports Gen 1 (1.5Gbps), Gen 2 (3.0Gbps), and Gen 3 (6.0Gbps) speeds.
  • Integrated Sandbox Logic: Transparent area for custom RTL insertion into the data path at line speed.
  • Command-Based Switching: Efficiently manages data flow between one host and up to 15 targets.
  • Automatic Speed Negotiation: Handles link training and speed synchronization across all ports in hardware.
  • Low Latency Cut-Through: Minimizes performance impact on command overhead and data transfers.
  • Full Feature Support: Compatible with NCQ (Native Command Queuing) and 48-bit LBA drives.
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Offering Brief

Offering Brief

Device Family Arria® 10 SX FPGA, Agilex™ 5 FPGA E-Series, Cyclone® V SX FPGA, Arria® V GZ FPGA, Agilex™ 7 FPGA I-Series, Arria® V SX FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX FPGA, Arria® 10 GT FPGA, Arria® V ST FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Agilex™ 5 FPGA D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Agilex™ 7 FPGA F-Series, Stratix® 10 AX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

SATA Port Multiplier IP Core: Encrypted RTL (Verilog/VHDL) optimized for Altera Quartus Prime Pro.

Sandbox Integration Templates: Documentation and RTL "hooks" for seamless custom logic insertion.

UVM Verification Suite: Comprehensive testbench including host and device models for pre-synthesis validation.

Reference Design: Complete Altera FPGA example project demonstrating multi-drive connectivity.

Technical Documentation: Detailed datasheet, integration guide, and register maps.

Ordering Information

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