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SAS 1 to 1 Speed Bridge with Sandbox (IPP-SS115A-BR)

IntelliProp: Experts in Memory and Data Storage IP

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The IntelliProp IPP-SS115A-BR SAS Speed Bridge is a silicon-proven IP core designed for high-throughput enterprise storage applications. This bridge facilitates seamless communication between SAS hosts and devices even when operating at different interface speeds.

A standout feature is the integrated 'Sandbox,' which provides developers with full visibility into the frame contents. This 'bump-in-the-wire' architecture allows for the insertion of custom hardware algorithms—such as line-speed encryption, data compression, or proprietary analytics—without disrupting the underlying SAS protocol.

Technical Highlights: Tri-Mode Support: Fully compliant with SAS-1 (3.0Gb/s), SAS-2 (6.0Gb/s), and SAS-3 (12.0Gb/s) specifications.

Hardware Sandbox: dedicated RTL area for custom logic insertion into the data path with cut-through FIFO architecture for ultra-low latency.

Protocol Transparency: Handles OOB (Out-of-Band) signaling...

The IntelliProp IPP-SS115A-BR SAS Speed Bridge is a silicon-proven IP core designed for high-throughput enterprise storage applications. This bridge facilitates seamless communication between SAS hosts and devices even when operating at different interface speeds.

A standout feature is the integrated 'Sandbox,' which provides developers with full visibility into the frame contents. This 'bump-in-the-wire' architecture allows for the insertion of custom hardware algorithms—such as line-speed encryption, data compression, or proprietary analytics—without disrupting the underlying SAS protocol.

Technical Highlights: Tri-Mode Support: Fully compliant with SAS-1 (3.0Gb/s), SAS-2 (6.0Gb/s), and SAS-3 (12.0Gb/s) specifications.

Hardware Sandbox: dedicated RTL area for custom logic insertion into the data path with cut-through FIFO architecture for ultra-low latency.

Protocol Transparency: Handles OOB (Out-of-Band) signaling, primitives, and Frame Information Structures (FIS) automatically.

Enterprise Reliability: Designed for mission-critical Data Center and AI storage environments using Altera Agilex™ and Stratix® FPGA families.

Key Features

  • 12G SAS Performance: Supports industry-standard 3.0, 6.0, and 12.0 Gb/s SAS interfaces (with speed-capable Altera FPGAs).
  • Speed-Independent Bridging: Allows independent speed negotiation on host and device connections, enabling older drives to work with modern high-speed hosts.
  • Inline Data Manipulation: The Sandbox allows customers to intercept, analyze, or modify SAS frames at line speed.
  • Automatic OOB & Speed Negotiation: Simplifies system integration by handling complex SAS link training automatically in hardware.
  • Low Latency Cut-Through: Optimized data movement between SAS cores minimizes performance impact on high-IOPS workloads.
  • Silicon-Proven IP: Extensively verified using coverage-driven UVM methodology and interoperability testing.
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Offering Brief

Offering Brief

Device Family Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Cyclone® V GX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

SAS Bridge IP Core: Encrypted Verilog RTL optimized for Altera Quartus Prime.

Sandbox Development Templates: RTL "hooks" and documentation for custom logic integration.

Comprehensive Verification Suite: ModelSim verification models, testbenches, and drive models.

Reference Design: Complete FPGA example project for rapid prototyping.

Technical Documentation: User Guides, Integration Manuals, and Register Maps.

Engineering Support: Design review and integration assistance from IntelliProp’s storage protocol experts.

Ordering Information

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