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SATA 1:1 Speed Bridge with Sandbox (IPP-SA110A-BR)

IntelliProp: Experts in Memory and Data Storage IP

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The IPP-SA110A-BR SATA Speed Bridge provides a robust solution for bridging SATA Generation 1 (1.5Gb/s), Generation 2 (3.0Gb/s), and Generation 3 (6.0Gb/s) power and data. Beyond simple speed adaptation, this IP features a unique 'Sandbox' architecture—a dedicated logic area that allows developers to insert custom hardware algorithms (such as encryption, data filtering, or real-time analytics) directly into the data path without impacting protocol integrity.

Technical Highlights: Automatic Speed Negotiation: Seamlessly bridges hosts and targets regardless of native SATA generation support.

Hardware Sandbox: Provides a transparent 'hook' for custom RTL, enabling inline data manipulation at line speed.

Low Latency Architecture: Optimized for Altera FPGA fabric to ensure minimal impact on IOPS and throughput.

Full Protocol Compliance: Compliant with SATA Revision 3.2 specifications, supporting NCQ and power management f...

The IPP-SA110A-BR SATA Speed Bridge provides a robust solution for bridging SATA Generation 1 (1.5Gb/s), Generation 2 (3.0Gb/s), and Generation 3 (6.0Gb/s) power and data. Beyond simple speed adaptation, this IP features a unique 'Sandbox' architecture—a dedicated logic area that allows developers to insert custom hardware algorithms (such as encryption, data filtering, or real-time analytics) directly into the data path without impacting protocol integrity.

Technical Highlights: Automatic Speed Negotiation: Seamlessly bridges hosts and targets regardless of native SATA generation support.

Hardware Sandbox: Provides a transparent 'hook' for custom RTL, enabling inline data manipulation at line speed.

Low Latency Architecture: Optimized for Altera FPGA fabric to ensure minimal impact on IOPS and throughput.

Full Protocol Compliance: Compliant with SATA Revision 3.2 specifications, supporting NCQ and power management features.

This IP is ideal for secure storage applications, industrial data logging, and legacy system modernization using Altera Agilex™ and Stratix® FPGAs.

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Key Features

  • SATA Generation Bridging: Supports seamless speed adaptation between SATA Gen 1 (1.5Gbps), Gen 2 (3.0Gbps), and Gen 3 (6.0Gbps) hosts and targets.
  • Integrated Hardware Sandbox: Features a dedicated, transparent logic area for the insertion of custom RTL (encryption, compression, or data filtering) without altering the SATA protocol.
  • Low Latency Passthrough: Optimized hardware architecture ensures minimal impact on command overhead and data throughput, maintaining high IOPS.
  • Full Protocol Transparency: Supports all mandatory SATA 3.2 features, including NCQ (Native Command Queuing), 48-bit LBA, and power management (Partial/Slumber).
  • Silicon-Proven IP: Heavily tested and verified on Altera Agilex™, Stratix®, and Arria® FPGA families for immediate integration.
  • Independent Clock Domains: Utilizes robust asynchronous FIFOs to manage data transfer between mismatched host and device clock speeds.
  • Automatic Link Negotiation: Smart speed-sensing logic automatically detects and configures the highest supported speed between the host and the drive.
  • Error Handling & Reporting: Comprehensive built-in error detection and status registers for link monitoring and simplified system debugging.
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Offering Brief

Offering Brief

Device Family Arria® 10 SX FPGA, Agilex™ 5 FPGA E-Series, Cyclone® V SX FPGA, Arria® V GZ FPGA, Agilex™ 7 FPGA I-Series, Arria® V SX FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX FPGA, Arria® 10 GT FPGA, Arria® V ST FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Agilex™ 5 FPGA D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Agilex™ 7 FPGA F-Series, Stratix® 10 AX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 25.3.0
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

SATA Bridge IP Core: Encrypted RTL or Netlist optimized for Altera Quartus Prime.

Sandbox Integration Kit: Documentation and RTL templates for inserting custom logic into the data path.

Reference Design: A complete FPGA project demonstrating the bridge functionality on Altera development kits.

Simulation Environment: A comprehensive Verilog/SystemVerilog testbench for pre-synthesis validation.

Technical Documentation: Detailed User Guide, Register Maps, and Integration Manual.

Engineering Support: Direct access to IntelliProp’s SATA experts for design review and integration assistance.

Ordering Information

IPP-SA110A-BR

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