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NAND Flash Controller

iWave Global

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iWave’s NAND Flash Controller IP Core provides a highly reliable and efficient solution for interfacing with raw NAND Flash memory devices. Designed to support SLC and MLC NAND Flash, the controller delivers flexibility across various storage applications where direct control of NAND Flash is required. The IP core abstracts low-level complexities and provides robust command and error-handling mechanisms, making it ideal for high-reliability systems such as industrial storage, automotive data logging, and embedded bootloaders.

This IP core supports a wide range of NAND Flash command sets and provides ECC (Error Correction Code) capabilities to ensure data integrity. The controller implements key features such as wear-leveling and bad block management and supports customizable timing parameters for compatibility with a wide range of NAND devices. With support for both AXI and Avalon interfaces, it integrates smoothly into Intel and other FPGA platforms.

Key Features

  • 8-bit Asynchronous Interface to NAND device
  • SLC NAND Flash Memory
  • Page Size: 2KByte
  • Separate Chip Select, Write Enable, Read Enable and Ready/Busy for each die and the IO signals are shared between the die
  • ECC Logic: Hamming code for 1-bit error correction and 2- bit error detection or BCH code which can correct up to 8 bit errors
  • Commands supported towards NAND Flash Memory: Read, Reset, Page Program, Block Erase and Read Status
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Offering Brief

Offering Brief

Device Family Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 GX FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Hardware Platforms Supported Arria® 10 GX FPGA Development Kit
Latest Quartus Version Supported 17.0.0
Development Language Verilog, VHDL

IP Core

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