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NVMe Host Controller

iWave Global

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iWave’s NVMe Host Controller IP Core is a high-performance, FPGA-optimized solution that facilitates direct interfacing with NVMe-based SSDs via PCIe. Fully compliant with the NVMe 1.4 specification, the IP core eliminates the need for external memory by utilizing on-chip resources, making it ideal for storage-centric applications with strict performance, space, and latency constraints.

Designed to function as an NVMe host, the core seamlessly integrates with user logic through AXI interfaces and supports flexible customization depending on the PCIe IP used. Its lightweight and low-latency architecture supports streamlined memory transfers and maximized throughput while minimizing design complexity. This makes the solution perfect for applications in data logging, industrial computing, and high-speed embedded storage.

The NVMe Host Controller IP Core enables FPGA-based systems to adopt the NVMe protocol in a scalable and efficient manner, accelerating time-to-market.

iWave’s NVMe Host Controller IP Core is a high-performance, FPGA-optimized solution that facilitates direct interfacing with NVMe-based SSDs via PCIe. Fully compliant with the NVMe 1.4 specification, the IP core eliminates the need for external memory by utilizing on-chip resources, making it ideal for storage-centric applications with strict performance, space, and latency constraints.

Designed to function as an NVMe host, the core seamlessly integrates with user logic through AXI interfaces and supports flexible customization depending on the PCIe IP used. Its lightweight and low-latency architecture supports streamlined memory transfers and maximized throughput while minimizing design complexity. This makes the solution perfect for applications in data logging, industrial computing, and high-speed embedded storage.

The NVMe Host Controller IP Core enables FPGA-based systems to adopt the NVMe protocol in a scalable and efficient manner, accelerating time-to-market.

Key Features

  • Admin Command Supported: SMART/Health information, Identify Controller data Structure, Identify Namespace data structure, Secure Erase, Shutdown command for efficient NVMe device management.
  • NVM Command Supported: Write Command, Read Command, Flush command for reliable and high-performance data transfer.
  • Operates with LBA size of 512 Bytes
  • Operates with Vendor specific PCIe Hard IP as a physical layer to access NVMe SSD
  • User data interface: AXI4 – Stream
  • User control interface: AXI4- Lite
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Hardware Platforms Supported Agilex™ 7 FPGA Starter Kit
Latest Quartus Version Supported 24.2.0
Development Language Verilog

IP Core

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments