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Parretto DisplayPort IP Core

Microtronix Datacom Ltd.

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The DisplayPort IP-core is a DisplayPort 1.4 solution for FPGA implementation. It has a resource optimized footprint and it is written in SystemVerilog. A thin host driver comes with the IP-core. The application software controls the IP-core through this driver.

Support for 1, 2 and 4 DP lanes in RBR, HBR, HBR2 and HBR3 line rates. Color depth is 8-bits and color space is RGB 4:4:4.

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Key Features

  • DisplayPort TX (DPTX) - SST
  • DisplayPort TX (DPTX) - MST
  • DisplayPort RX (DPRX)
  • Video Toolbox (VTB)

Offering Brief

Offering Brief

Device Family Agilex® 3 FPGAs and SoC FPGAs C-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 23.2.0
Development Language C/C++, Verilog

IP-core is available as both source (DPTX) and sink (DPRX)

Ordering Information

5311-00-00

from Direct

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Documentation & Resources

design hub icon Display Port Manual

Market Segment and Sub-Segments

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Broadcast

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Broadcast

Broadcast Studio

ProAV

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Medical

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Medical

Video

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