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100G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

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UDP/IP Full Accelerator for 100G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra-low Latency.

Key Features

  • Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
  • Full line rate of 70 Gbps or more in FPGA, 100 Gbps or more in ASIC
  • 128-bit wide bi-directional data paths with streaming interfaces
  • Multiple, parallel TCP engines for scalable processing
  • Network Interface Card functionality with Bypass (optional)
  • DPDK Stream interface (optional)
  • Corundum NIC integration with performance DMA and PCIe (optional)
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Offering Brief

Offering Brief

Device Family Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Cyclone® 10 GX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Evaluation License Yes
Design Examples Available Yes
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Modular and application-specific 100G UDP IP Core, and example design projects

Single-Project or Multi-Project Use for ASIC or FPGA

Delivered as encrypted netlists or RTL

Ordering Information

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