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DDR5/4 and LPDDR3/2 Controller (Silicon Proven IP for Altera Devices)

Mobiveil Inc.

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Highly configurable multi-port DDR/LPDDR/RLDRAM memory controller with AXI4 system interface (up to 32 ports), DFI 3.1/5.1 PHY interface, JEDEC-compliant DDR5/DDR4/DDR4-3DS/LPDDR3/LPDDR2 support, and architecture tuned for high frequency, low power, and rapid debug. UMMC is technology-independent, system-validated RTL that decouples application logic from the PHY via DFI 3.1/5.1, supports 8–64-bit data widths (DDR/LPDDR) and x9/x18/x36 (RLDRAM2/3), chip-select interleaving, and AXI4 multi-port (up to 32). It implements rich QoS arbitration, 1:1 / 1:2 / 1:4 MC:PHY clock ratios, separate read/write queues, out-of-order AXI IDs, and extensive power features (self-refresh, partial-array self-refresh, per-/multi-bank refresh, active/precharge/deep power-down). Delivered with configurable RTL, HDL testbench/behavioral models, protocol checkers, performance monitors, and design/verification/synthesis guides.

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Key Features

  • Compliant with AXI4 specification
  • Compliant with DFI 3.1/5.1 specification
  • RLDRAM2/RLDRAM3 support and JEDECcompliant DDR5, DDR4 3DS, DDR4, LPDDR2, LPDDR3
  • Supports memory data width from 8 to 64 bits for DDR4-3DS LPDDR2 & LPDDR3 and x9, x18, x36 devices in any combined data width for RLDRAM2 & RLDRAM3
  • Supports chip select interleaving
  • Supports single and multi-port host buses AMBA4 AXI upto 32 ports
  • Supports multiple ranks with 16/8/4 banks per rank and configurable AXI address width.
  • Provides configurable request queue depth, write/read FIFO sizes, and QoS through various arbitration schemes.
  • Supports MC-to-PHY clock ratios of 1:1 (full-rate), 1:2 (half-rate), and 1:4 (quarter-rate) modes.
  • Enables self-refresh, partial array self-refresh, auto-refresh, per-bank refresh, and multi-bank refresh (RLDRAM).
  • Offers various power-down modes including active, precharge, and deep power-down.
  • Incorporates intelligent request scheduling and look-ahead command processing for maximum bus efficiency with bank-level parallelism.
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Configurable RTL Code

HDL-based test bench and behavioural models

Test cases

Protocol checkers, bus watchers and performance monitors

Configurable synthesis shell

Design Guide

Verification Guide

Synthesis Guide

Ordering Information

NA

from Direct

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