partner-offering-banner.png

LDPC for 5G NR (Silicon Proven IP for Altera Devices)

Mobiveil Inc.

Select

Configurable 5G NR LDPC encoder/decoder IP compliant with 3GPP TS 38.212 (Rel-17), supporting Base Graphs 1 & 2, wide lifting sizes (2–384), early-termination, and runtime-configurable code length/rate for high-throughput, low-latency 5G designs. Technology-independent, system-validated LDPC core for 5G NR PDSCH/PUSCH that implements min-sum decoding with programmable internal/LLR widths, HARQ combining, per-block selectable CB length / code rate / base graph / max iterations, and early exit via concurrent parity checks. Deliverables include synthesizable parameterized Verilog, synthesis scripts, UVM testbench & regression, test-vector software, C++ bit-accurate model, and documentation. Throughput scales with iterations and parallelism (graphs provided at 400 MHz clk).

View Partner Website Right arrow Right arrow Partner Product Page Right arrow Right arrow Contact Now

Key Features

  • Full support of 5G NR specification (38.212 v17)
  • Support for all Base Graphs 1/2 codes
  • Additional Measurement Outputs (number of iterations, other) beyond the scope of 5G physical channel measurement specified in 38.215
  • Per-block modifiable code block length, code rate, base graph, and maximum number of iterations
  • Supports for lifting sizes from 2 to 384
  • Early termination based on syndrome check on each iteration and layer
  • Supports FPGA, ASIC Platforms
  • Testbench option
Expand Close
Keyfeatures main image

Offering Brief

Offering Brief

Device Family Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Synthesizable parametrized Verilog

Synthesis scripts

Test-bench and regression test suite

Software for generating test vectors

C++ bit-accurate model

Documentation

Ordering Information

NA

from Direct

Get Pricing and Availability

Documentation & Resources

design hub icon LDPC for 5G NR - Product Brief

Market Segment and Sub-Segments

ASIC-Proto-252x228

ASIC Proto

View Sub-Segments

ASIC Proto

ASIC Emulation

ASIC Prototyping

Back to Market
Data-Center-Cloud-252x228

Data Center Cloud (Public, Private, Hybrid)

View Sub-Segments

Data Center Cloud (Public, Private, Hybrid)

Networking

Back to Market
Data-Center-OEM-252x228

Data Center OEM (IHV, ISV, SI, VAR)

View Sub-Segments

Data Center OEM (IHV, ISV, SI, VAR)

AI/HPC

Networking

Back to Market
Robotics-252x228

Industrial

View Sub-Segments

Industrial

Industrial / Manufacturing

Robotics

Vision

Back to Market
MMW

Wireless

View Sub-Segments

Wireless

5G/ 6G Radio

AI-RAN

Baseband

Back to Market