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Universal Time Sync (UTS) Complete Synchronization solution as combination of our IP cores

NetTimeLogic GmbH

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The Universal Time Sync (UTS) is an all-in-one time synchronization solution which allows you to create your synchronization system like a PTP Grandmaster, NTP Server, Time-Bridge or Multi-Source Time Sink with minimal effort and costs. It is the swiss-army-knife of synchronization. The UTS core consists of several subcores which can be tailored as needed.

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Key Features

  • Any Synchronization Core from NetTimeLogic can be combined as required
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Evaluation License Yes
Design Examples Available Yes
Latest Quartus Version Supported 25.1.0
OS Support Linux
Development Language VHDL

Source Code, Drivers

Ordering Information

NTl_UTS

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Documentation & Resources

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Market Segment and Sub-Segments

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Access

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