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CVI - Customizable Video Input Controller IP Core Family

TES Electronic Solutions GmbH

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CVI is a fully Customizable Video Input controller IP core. The video input controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.

The main functionality of CVI is reading an ITU-656 video input stream typically coming from a physical video input interface, e.g. a LVDS PHY or a video ADC, and writing the video data in RGB format to memory via DMA. Several on-the-fly operations on the video data can be applied such as clipping, scaling, color conversion, gamma correction, dithering and de-interlacing.

On the input side CVI can accept RGB as well as YCbCr color formats, in the latter case applying the on-the-fly conversion from YCbCr to RGB.

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Key Features

  • ITU-656 Video Capture
  • On-the-fly color space conversion
  • Scaling, Clipping, Dithering
  • Deinterlacing
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 Bare Die, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® II GZ FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® III Bare Die, Cyclone® III FPGA, Cyclone® III LS FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, HardCopy™ III ASIC Devices, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 Bare Die, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GT FPGA, Stratix® IV GX FPGA, Stratix® V E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, eASIC™ N3X Devices, eASIC™ N3XS Devices, eASIC™ N5X Devices
Offering Status Production
Integrated Testbench No
Evaluation License Yes
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 24.1.0
Development Language Encrypted VHDL, VHDL

Q-Sys Component or (on demand) VHDL source code

Bare metal driver

Documentation

Ordering Information

CVI

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Documentation & Resources

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Market Segment and Sub-Segments

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