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H16450S: UART with Synchronous CPU Interface

Computer Aided Software Technologies, Inc (dba CAST)

Member

The H16450S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16450 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. Developed for easy reuse in ASIC and FPGA applications, the H16450S is available optimized for several technologies with competitive utilization and performance characteristics.

Key Features

  • Capable of running all existing 16450 software
  • Fully Synchronous design. All inputs and outputs are based on rising edge of clock
  • Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
  • Independently controlled transmit, receive, line status and data set interrupts
  • Programmable baud generator divides any input clock by 1 to (2^16 - 1) and generates the 16x clock
  • Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn, and DCDn)
  • Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn, and DCDn)
  • False start bit detection; complete status register
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGA C-Series, Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Compliance Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Verilog/System Verilog, Encrypted Verilog/System Verilog, VHDL, Encrypted VHDL, or FPGA netlist

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments