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50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

Missing Link Electronics

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Core Benefits: Accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic (“Offloading”). Increase network throughput and reduce transport latency. Bring full TCP/UDP/IP connectivity to FPGAs even if no CPU is available (“Full Acceleration”). Complete and customizable turn-key solutions and IP cores based on the TCP/UDP/IP stack from the Fraunhofer HHI. All MAC/Ethernet/IPv4/UDP/TCP processing is implemented in HDL code, synthesizable to modern FPGAs and ASIC. User applications can either be implemented in FPGA logic or in software via application-specific interfaces to CPUs.

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Key Features

  • Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
  • Full line rate of 70 Gbps or more in FPGA, 100 Gbps or more in ASIC
  • 128-bit wide bi-directional data paths with streaming interfaces
  • Multiple, parallel TCP engines for scalable processing
  • Network Interface Card functionality with Bypass (optional)
  • DPDK Stream interface (optional)
  • Corundum NIC integration with performance DMA and PCIe (optional)
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Offering Brief

Offering Brief

Device Family Agilex® 5 FPGA D-Series, Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series, Agilex® 9 FPGA Direct RF-Series, Cyclone® 10 GX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® III FPGA, Stratix® IV GX FPGA, Stratix® V GX FPGA
Offering Status Production
Design Examples Available Yes
Latest Quartus Version Supported 25.1.1
Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL

Single-Project or Multi-Project Use for ASIC or FPGA

Modular and application-specific IP cores, and example design projects

Delivered as encrypted netlists or RTL

Ordering Information

npap-50g

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