Mixed Signal FPGAs (ADC/DAC) - MLE FPGA IP Core Design Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets Missing Link Electronics Select MLE Mixed Signal FPGAs: - No active peripheral components, analog I/Os are directly integrated into the FPGA - Reduced parts count and PCB footprint - Enables simultaneous and time-synchronous sampling, direct and straightforward View Partner Website Partner Product Page Contact Now Contact Missing Link Electronics X You must have JavaScript enabled to use this form. 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I agree to receive marketing communications from Altera Corporation. I understand I can unsubscribe at any time and that my information will be handled in accordance with the [Privacy Policy]. We collect personal information from you, including identifiers and geolocation data, to enhance your experience, provide customer support, and analytics. We may share this data with third-party providers. For more information, please see our Privacy Policy. LeadSource - None -Market Place ASAP Account ID Record Type Name Leave this field blank Key Features Reduce your hardware footprint and parts count No active peripheral ICs required Efficient post-processing with low FPGA resource cost. Highly reconfigurable analog-to-digital converter (ADC) / digital-to-analog converter (DAC) parameter setting Design flexibility: „one more I/O“ Greatly reduce costs when applying multitudes of analog I/O channels Reasonable I/O precision, more than sufficient for most of today’s analog applications in Embedded Systems ADC sample rate: up to 200 kS/s ADC resolution: up to 11 bits ENOB Offering Brief Offering Brief Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GX FPGA, Arria® V GX FPGA, Cyclone® 10 GX FPGA, Cyclone® IV GX FPGA, Cyclone® V GX FPGA, Stratix® III FPGA, Stratix® IV GX FPGA, Stratix® V GX FPGA Offering Status Production Design Examples Available Yes Latest Quartus Version Supported 25.1.1 Development Language Encrypted Verilog, Encrypted VHDL, Verilog, VHDL What’s Included? IP license for one defined product (worldwide, fully paid up for, perpetual) Up to 3 parametrizations, up to 33 channels per FPGA device family Ordering Information mixed-signal from Direct Documentation & Resources Product Brochure Application Note: Integrated ADC for Altera Cyclone-IV Devices Application Note: Integrated DAC for Altera Cyclone-IV Devices Market Segment and Sub-Segments Aerospace View Sub-Segments Aerospace Aerospace Back to Market Defense View Sub-Segments Defense MIL COMMS Radar/Ew Back to Market Offering Types and Sub-Types Design Services Board Level Design FPGA Design Intellectual Property (IP) Interfaces Communication High Speed