partner-offering-banner.png

CXL 3.x

Qbit Labs Incorporation

Member

The Compute Express Link™ (CXL) 3.x IP Core is designed to meet the demands of next-generation heterogeneous computing systems, enabling high-speed, low-latency interconnect between CPUs, GPUs, FPGAs, DPUs, accelerators, memory expanders, and smart I/O devices.

Supporting the CXL 3.0 specification, this IP delivers backward compatibility with CXL 1.x/2.0, advanced memory pooling, and fabric capabilities, making it ideal for data centers, AI/ML workloads, and HPC environments.

Key Features

  • CXL Protocol Support: CXL.io, CXL.cache, and CXL.mem coherence protocols with support for Type 1, Type 2, and Type 3 devices.
  • Backward Compatibility: Fully compliant with CXL 1.1 and CXL 2.0 for smooth ecosystem integration.
  • High Bandwidth: Leverages PCIe 6.0 physical layer for up to 64 GT/s per lane with PAM4 signaling.
  • Scalability: Supports up to 16-lane configurations for maximum throughput and bandwidth aggregation.
  • Flexible Integration: Modular design supporting multiple SoC and FPGA platforms with AXI interfaces.
Expand Close
Keyfeatures main image

Offering Brief

Offering Brief

Device Family Agilex® 5 FPGA E-Series, Agilex® 7 FPGA F-Series, Agilex® 7 FPGA I-Series, Agilex® 7 FPGA M-Series
Offering Status Production
Evaluation License Yes
Design Examples Available Yes
Compliance Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Synthesizable encrypted RTL source code

Embedded firmware / low-level SW

CXL Controller Requirements Specification (CRS)

CXL Controller Micro-Architecture Specification

CXL Controller Programmer’s Reference Manual (PRM)

Synthesizable RTL source code (Verilog/SystemVerilog preferred; VHDL if requested) covering: CXL.io (PCIe-compatible Transaction/Data Link/Port layers). CXL.cache and CXL.mem protocols (link layer, transaction layer, coherency handling). Arb/MUX logic for protocol multiplexing. Low-latency features (e.g., alternate protocol negotiation, vLSMs, zero-added-latency paths in CXL 3.x). Reliability (RAS: FEC, CRC, poison handling), error reporting, AER.

Ordering Information

Market Segment and Sub-Segments