Aurora 8B/10B IP Core

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

ALSE Advanced Logic Synthesis for Electronics

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The ALSE IP provides an efficient way to interconnect an Altera FPGA with a Xilinx/AMD FPGA. Complete interoperability with the Xilinx IP is guaranteed. It can also be used to interconnect two Altera FPGAs together, in replacement of other proprietary or complex High-Speed Serial protocols (like Serial Lite IV or PCIExpress). Another use case would be an Altera High-End or mid-range FPGA to low cost or very low power FPGA from another vendor.

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Key Features

Aurora 8B/10B complete protocol support with all configuraitons

Offering Brief

Device Family	Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	Yes
Demo	No
Compliance	No
Intertop	with Xilinx IP
Latest Quartus Version Supported	25.3.1
OS Support	Linux,Windows
Development Language	Encrypted VHDL, Other