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PCIe Gen 6

Qbit Labs Incorporation

Member

The PCIe Gen 6 offering provides an ultra-high-performance, standards-compliant connectivity solution delivering data rates up to 64 GT/s per lane, doubling the bandwidth of PCIe Gen5 to address the most demanding, data-intensive applications. It is engineered to support next-generation servers, AI/ML accelerators, high-performance storage, networking platforms, and advanced embedded systems requiring extremely low latency, exceptional throughput, and enhanced signal integrity.

Leveraging PAM4 signaling, FLIT-based architecture, and Forward Error Correction (FEC), the solution ensures reliable and efficient data transmission at very high speeds while maintaining backward compatibility with earlier PCIe generations. It enables highly scalable system architectures, supporting multi-lane configurations for massive aggregate bandwidth, and integrates seamlessly into modern data centers, hyperscale computing, cloud infrastructure, and high-performance computi...

The PCIe Gen 6 offering provides an ultra-high-performance, standards-compliant connectivity solution delivering data rates up to 64 GT/s per lane, doubling the bandwidth of PCIe Gen5 to address the most demanding, data-intensive applications. It is engineered to support next-generation servers, AI/ML accelerators, high-performance storage, networking platforms, and advanced embedded systems requiring extremely low latency, exceptional throughput, and enhanced signal integrity.

Leveraging PAM4 signaling, FLIT-based architecture, and Forward Error Correction (FEC), the solution ensures reliable and efficient data transmission at very high speeds while maintaining backward compatibility with earlier PCIe generations. It enables highly scalable system architectures, supporting multi-lane configurations for massive aggregate bandwidth, and integrates seamlessly into modern data centers, hyperscale computing, cloud infrastructure, and high-performance computing (HPC) environments.

Key Features

  • PCI Express 6.0 Specification Compliant: Fully compliant with PCIe Base Specification Revision 6.0.
  • PAM4 Signaling Support: Enables 64 GT/s raw data rate per lane.
  • FLIT Mode Support: Implements Flow Control Unit (FLIT) encoding and decoding.
  • Scalable Lane Configurations: Supports x1, x2, x4, x8, and x16 with dynamic lane reversal and polarity inversion.
  • Robust Error Handling: Implements CRC, ECC, and ECRC for reliable data transmission.
  • Low Power Architecture: Designed with advanced clock gating and dynamic power management
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Offering Brief

Offering Brief

Device Family Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series
Offering Status Production
Integrated Testbench No
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Synthesizable encrypted RTL source code

Directed/random/constrained-random sequences covering LTSSM, configuration, link training, FLIT mode, error injection (FEC/CRC scenarios), power states, reset.

Embedded firmware / low-level SW

Software integration guide

Full design documentation

FPGA bitstream/prototyping support

Ordering Information

Market Segment and Sub-Segments