10G/100G MAC/PCS IP

Overview Key Features Offering Brief What's Included Ordering Information Markets

Qbit Labs Incorporation

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The 10G/100G MAC/PCS IP Core is a fully integrated and configurable solution that combines the Ethernet Media Access Control (MAC) and Physical Coding Sublayer (PCS) functionality into a single, high-performance IP block.

Designed in compliance with IEEE 802.3ae (10G) and IEEE 802.3ba (100G) standards, this IP core is ideal for implementing high-speed Ethernet solutions in FPGAs and ASICs for data center, telecom, AI, and networking infrastructure applications.

The IP core handles Ethernet frame encapsulation, error checking, flow control, lane alignment, and 64b/66b encoding/decoding — all with deterministic performance and minimal resource overhead.

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Key Features

IEEE 802.3ae and 802.3ba Compliant: Fully compliant with 10G and 100G Ethernet MAC and PCS specifications.
Integrated 64b/66b Encoding & Decoding: Implements the PCS sublayer for lane encoding, synchronization, and scrambling.
High-Speed Operation: Supports full-duplex operation at 10 Gbps and 100 Gbps line rates.
Pause Frame Support (802.3x): Flow control via pause frame generation and handling to manage congestion.
Jumbo Frame Support: Configurable support for standard and oversized Ethernet frames.

Offering Brief

Device Family	Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted Verilog, Verilog

Synthesizable RTL source code

Directed/random/constrained-random sequences covering LTSSM, configuration, link training, FLIT mode, error injection (FEC/CRC scenarios), power states, reset

Embedded firmware / low-level SW

Software integration guide

Full design documentation