P4 Suite for Altera

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Pantherun Technologies

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The P4 Suite for FPGA is a high-level design tool that enables rapid development of custom networking data plane functionality using the P4 programming language. P4 is an open-source, domain-specific language designed to describe how a packet is processed by a data plane device.

The P4 Suite for FPGA automates the generation of packet-processing RTL intellectual property (IP) and supports deployment across a wide range of networking hardware and software platforms.

Design network applications with minimal hardware expertise using the industry-standard P4 language enabling protocol independence, flexible customization, simplified hardware abstraction, enhanced performance, and reduced system cost with Altera FPGAs.

It supports fully custom P4 Architectures, providing enhanced flexibility and custom IP interoperability. This allows for optimized performance and cost efficiency, enabling adaptable, efficient performance-optimized network solutions.

The P4 Suite for FPGA automates the generation of packet-processing RTL intellectual property (IP) and supports deployment across a wide range of networking hardware and software platforms.

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Device Family	Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA
Offering Status	Production

A compiler that translates P4 programs into synthesizable RTL

An FPGA software framework that provides a runtime application programming interface (API) to control the generated RTL logic

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