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JPEG-XL-E JPEG XL Encoder

Computer Aided Software Technologies, Inc (dba CAST)

Member

The JPEG-XL-E implements an image compression engine compliant to the JPEG XL, ISO/IEC 18181 standard. Leveraging the advanced coding tools of the JPEG XL standard, the core achieves substantially higher compression efficiency than legacy JPEG while requiring fewer hardware resources than JPEG 2000 and comparable codecs. By incorporating algorithms optimized for human visual perception, it delivers exceptional performance for high dynamic range (HDR) and wide color gamut (WCG) imagery.

Thanks to its efficient architecture, the compact encoder core achieves a latency of just one frame and a processing throughput of one sample per clock cycle. A single instance can encode 4K-resolution images in real time, while multiple cores can be instantiated in parallel to support higher resolutions. The JPEG-XL-E core accepts input samples in IEEE 754 single- or half-precision floating-point format and outputs the JPEG XL compressed payload.

Designed for ease ...

The JPEG-XL-E implements an image compression engine compliant to the JPEG XL, ISO/IEC 18181 standard. Leveraging the advanced coding tools of the JPEG XL standard, the core achieves substantially higher compression efficiency than legacy JPEG while requiring fewer hardware resources than JPEG 2000 and comparable codecs. By incorporating algorithms optimized for human visual perception, it delivers exceptional performance for high dynamic range (HDR) and wide color gamut (WCG) imagery.

Thanks to its efficient architecture, the compact encoder core achieves a latency of just one frame and a processing throughput of one sample per clock cycle. A single instance can encode 4K-resolution images in real time, while multiple cores can be instantiated in parallel to support higher resolutions. The JPEG-XL-E core accepts input samples in IEEE 754 single- or half-precision floating-point format and outputs the JPEG XL compressed payload.

Designed for ease of integration, the encoder core operates autonomously once configured, requiring no further assistance from the host processor. It provides 64-bit AMBA® AXI manager interfaces for reading uncompressed image data and writing the compressed bitstream to system memory, as well as an APB3 subordinate interface for control and status register access.

JPEG-XL-E is designed with industry best practices, and its reliability has been proven through both rigorous verification and extensive prototype testing. Its deliverables include a complete verification environment and a bit-accurate software model.

Key Features

  • Higher compression efficiency than JPEG with near-lossless visual quality, reducing bandwidth and storage while preserving image fidelity
  • Real-time performance with one sample per cycle and one-frame latency, enabling 4K encoding and scalable throughput for high-res systems
  • Exceptional support for HDR and wide color gamut, preserving rich colors and dynamic range for modern imaging and professional applications
  • Easy SoC integration via AXI4/APB interfaces with autonomous operation and a processor free design
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Offering Brief

Offering Brief

Device Family Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® II GX FPGA, Arria® II GZ FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE FPGA, Cyclone® V ST FPGA, Cyclone® V SX FPGA, MAX® 10 FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

Verilog/System Verilog, Encrypted Verilog/System Verilog or FPGA netlist

Sample integration testbench

Comprehensive documentation

Sample synthesis and simulation scripts

Bit-Accurate software model

IPxact register models

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments