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H265 Video Encoder

System-On-Chip Technologies Inc.

Member

SOC's HD H.265/HEVC encoder IP cores provide higher compression efficiency, significantly reducing bandwidth requirements while offering enhanced computational performance. Leveraging SOC's all-hardware architecture and efficient design methodology, these cores deliver optimal performance. All-hardware design (no embedded software)

High Speed (Low latency)

Small Silicon Footprint

Low Power

High Reliability (due to hardware architecture)

High-Video Quality

Low Output Bandwidth

High-Output Bandwidth Version Available

User Controllable API

Key Features

  • Low Latency
  • Runtime API
  • Higher video Quality
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Keyfeatures main image

Offering Brief

Offering Brief

Device Family Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.0
Development Language Encrypted VHDL

Netlist or Encrypted HDL

Integration Guide

API Register MAP

Sample Integration

Ordering Information

Documentation & Resources

Market Segment and Sub-Segments