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H265 Video Decoder

System-On-Chip Technologies Inc.

Member

SOC's H.265/HEVC decoder IP cores provide higher compression efficiency, significantly reducing bandwidth requirements while offering enhanced computational performance. Leveraging SOC's all-hardware architecture and efficient design methodology, these cores deliver optimal performance. All-hardware design (no embedded software)

High Speed (Low latency)

Small Silicon Footprint

Low Power

High Reliability (due to hardware architecture)

High-Video Quality

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Key Features

  • Fabric Only IP Core
  • Low Latency
  • Progressive and Interlaced
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Offering Brief

Offering Brief

Device Family Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.0
Development Language Encrypted VHDL

IP Core

Integration Guide

API Register Map

Sample Integration system

Ordering Information

DC-H265-IPCORE

from Direct

$0.00

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Documentation & Resources

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