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MPEG2 Video Decoder

System-On-Chip Technologies Inc.

Member

The MPEG-2 Video Decoder IP Core delivers high-performance encoding for single or multiple MPEG-2 video streams. Built on an all-hardware, highly parallel architecture, these processor-free CODEC IP Cores are engineered for superior efficiency. All-hardware design (no embedded software)

High Speed (Low latency)

Small Silicon Footprint

Low Power

High Reliability

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Key Features

  • Low Resources
  • Fabric Only Core
  • Interlaced and Progressive support
  • Low Latency
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Offering Brief

Offering Brief

Device Family Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST FPGA, Arria® V SX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® V E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo No
Compliance No
Latest Quartus Version Supported 24.3.0
Development Language Encrypted VHDL

IP Core

Integration Guide

API Register Map

Sample Integration

Ordering Information

DC-MPEG2-IPCORE

from Direct

$0.00

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Documentation & Resources

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